Discussion:
[PATCH 1/4] radeonsi/gfx9: disable sparse buffers
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Marek Olšák
2017-06-17 13:44:31 UTC
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From: Marek Olšák <***@amd.com>

---
src/gallium/drivers/radeonsi/si_pipe.c | 3 +++
1 file changed, 3 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 9d9cbd4..2b39ed0 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -558,20 +558,23 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
/* SI doesn't support unaligned loads.
* CIK needs DRM 2.50.0 on radeon. */
return sscreen->b.chip_class == SI ||
(sscreen->b.info.drm_major == 2 &&
sscreen->b.info.drm_minor < 50);

case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
+ /* TODO: GFX9 hangs. */
+ if (sscreen->b.chip_class >= GFX9)
+ return 0;
/* Disable on SI due to VM faults in CP DMA. Enable once these
* faults are mitigated in software.
*/
if (sscreen->b.chip_class >= CIK &&
sscreen->b.info.drm_major == 3 &&
sscreen->b.info.drm_minor >= 13)
return RADEON_SPARSE_PAGE_SIZE;
return 0;

/* Unsupported features. */
--
2.7.4
Marek Olšák
2017-06-17 13:44:32 UTC
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From: Marek Olšák <***@amd.com>

---
src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
index e72052c..3b50ca5 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
@@ -1486,21 +1486,22 @@ static void tex_fetch_args(
if (num_coords > 1)
address[count++] = coords[1];
if (num_coords > 2)
address[count++] = coords[2];

/* 1D textures are allocated and used as 2D on GFX9. */
if (ctx->screen->b.chip_class >= GFX9) {
LLVMValueRef filler;

/* Use 0.5, so that we don't sample the border color. */
- if (opcode == TGSI_OPCODE_TXF)
+ if (opcode == TGSI_OPCODE_TXF ||
+ opcode == TGSI_OPCODE_TXF_LZ)
filler = ctx->i32_0;
else
filler = LLVMConstReal(ctx->f32, 0.5);

if (target == TGSI_TEXTURE_1D ||
target == TGSI_TEXTURE_SHADOW1D) {
address[count++] = filler;
} else if (target == TGSI_TEXTURE_1D_ARRAY ||
target == TGSI_TEXTURE_SHADOW1D_ARRAY) {
address[count] = address[count - 1];
--
2.7.4
Marek Olšák
2017-06-17 13:44:34 UTC
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From: Marek Olšák <***@amd.com>

GFX9 is affected.
---
src/gallium/drivers/radeonsi/si_blit.c | 36 ++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
index 1159594..b78fddf 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -1133,20 +1133,56 @@ void si_resource_copy_region(struct pipe_context *ctx,
src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
break;
default:
fprintf(stderr, "Unhandled format %s with blocksize %u\n",
util_format_short_name(src->format), blocksize);
assert(0);
}
}
}

+ /* SNORM8 blitting has precision issues on some chips. Use the SINT
+ * equivalent instead, which doesn't force DCC decompression.
+ * Note that some chips avoid this issue by using SDMA.
+ */
+ if (util_format_is_snorm8(dst_templ.format)) {
+ switch (dst_templ.format) {
+ case PIPE_FORMAT_R8_SNORM:
+ dst_templ.format = src_templ.format = PIPE_FORMAT_R8_SINT;
+ break;
+ case PIPE_FORMAT_R8G8_SNORM:
+ dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8_SINT;
+ break;
+ case PIPE_FORMAT_R8G8B8X8_SNORM:
+ dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8B8X8_SINT;
+ break;
+ case PIPE_FORMAT_R8G8B8A8_SNORM:
+ case PIPE_FORMAT_A8B8G8R8_SNORM: /* also swizzle */
+ case PIPE_FORMAT_X8B8G8R8_SNORM: /* also swizzle */
+ dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8B8A8_SINT;
+ break;
+ case PIPE_FORMAT_A8_SNORM:
+ dst_templ.format = src_templ.format = PIPE_FORMAT_A8_SINT;
+ break;
+ case PIPE_FORMAT_L8_SNORM:
+ dst_templ.format = src_templ.format = PIPE_FORMAT_L8_SINT;
+ break;
+ case PIPE_FORMAT_L8A8_SNORM:
+ dst_templ.format = src_templ.format = PIPE_FORMAT_L8A8_SINT;
+ break;
+ case PIPE_FORMAT_I8_SNORM:
+ dst_templ.format = src_templ.format = PIPE_FORMAT_I8_SINT;
+ break;
+ default:; /* fall through */
+ }
+ }
+
vi_disable_dcc_if_incompatible_format(&sctx->b, dst, dst_level,
dst_templ.format);
vi_disable_dcc_if_incompatible_format(&sctx->b, src, src_level,
src_templ.format);

/* Initialize the surface. */
dst_view = r600_create_surface_custom(ctx, dst, &dst_templ,
dst_width0, dst_height0,
dst_width, dst_height);
--
2.7.4
Nicolai Hähnle
2017-06-19 12:56:06 UTC
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Post by Marek Olšák
GFX9 is affected.
---
src/gallium/drivers/radeonsi/si_blit.c | 36 ++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
index 1159594..b78fddf 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -1133,20 +1133,56 @@ void si_resource_copy_region(struct pipe_context *ctx,
src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
break;
fprintf(stderr, "Unhandled format %s with blocksize %u\n",
util_format_short_name(src->format), blocksize);
assert(0);
}
}
}
+ /* SNORM8 blitting has precision issues on some chips. Use the SINT
+ * equivalent instead, which doesn't force DCC decompression.
+ * Note that some chips avoid this issue by using SDMA.
+ */
+ if (util_format_is_snorm8(dst_templ.format)) {
+ switch (dst_templ.format) {
+ dst_templ.format = src_templ.format = PIPE_FORMAT_R8_SINT;
+ break;
+ dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8_SINT;
+ break;
+ dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8B8X8_SINT;
+ break;
+ case PIPE_FORMAT_A8B8G8R8_SNORM: /* also swizzle */
+ case PIPE_FORMAT_X8B8G8R8_SNORM: /* also swizzle */
+ dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8B8A8_SINT;
Why does R8G8B8X8 need a separate case but not X8B8G8R8?

Do we have a test for this?

Cheers,
Nicolai
Post by Marek Olšák
+ break;
+ dst_templ.format = src_templ.format = PIPE_FORMAT_A8_SINT;
+ break;
+ dst_templ.format = src_templ.format = PIPE_FORMAT_L8_SINT;
+ break;
+ dst_templ.format = src_templ.format = PIPE_FORMAT_L8A8_SINT;
+ break;
+ dst_templ.format = src_templ.format = PIPE_FORMAT_I8_SINT;
+ break;
+ default:; /* fall through */
+ }
+ }
+
vi_disable_dcc_if_incompatible_format(&sctx->b, dst, dst_level,
dst_templ.format);
vi_disable_dcc_if_incompatible_format(&sctx->b, src, src_level,
src_templ.format);
/* Initialize the surface. */
dst_view = r600_create_surface_custom(ctx, dst, &dst_templ,
dst_width0, dst_height0,
dst_width, dst_height);
--
Lerne, wie die Welt wirklich ist,
Aber vergiss niemals, wie sie sein sollte.
Marek Olšák
2017-06-19 14:15:38 UTC
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Post by Nicolai Hähnle
Post by Marek Olšák
GFX9 is affected.
---
src/gallium/drivers/radeonsi/si_blit.c | 36
++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/si_blit.c
b/src/gallium/drivers/radeonsi/si_blit.c
index 1159594..b78fddf 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -1133,20 +1133,56 @@ void si_resource_copy_region(struct pipe_context *ctx,
src_templ.format =
PIPE_FORMAT_R32G32B32A32_UINT;
break;
fprintf(stderr, "Unhandled format %s with
blocksize %u\n",
util_format_short_name(src->format), blocksize);
assert(0);
}
}
}
+ /* SNORM8 blitting has precision issues on some chips. Use the
SINT
+ * equivalent instead, which doesn't force DCC decompression.
+ * Note that some chips avoid this issue by using SDMA.
+ */
+ if (util_format_is_snorm8(dst_templ.format)) {
+ switch (dst_templ.format) {
+ dst_templ.format = src_templ.format =
PIPE_FORMAT_R8_SINT;
+ break;
+ dst_templ.format = src_templ.format =
PIPE_FORMAT_R8G8_SINT;
+ break;
+ dst_templ.format = src_templ.format =
PIPE_FORMAT_R8G8B8X8_SINT;
+ break;
+ case PIPE_FORMAT_A8B8G8R8_SNORM: /* also swizzle */
+ case PIPE_FORMAT_X8B8G8R8_SNORM: /* also swizzle */
+ dst_templ.format = src_templ.format =
PIPE_FORMAT_R8G8B8A8_SINT;
Why does R8G8B8X8 need a separate case but not X8B8G8R8?
There are no SINT variants for ABGR and XBGR, so we have to use RGBA.
Post by Nicolai Hähnle
Do we have a test for this?
We only have tests for GL_x_SNORM where x is R8, RG8, RGB8, and RGBA8.

Marek
Nicolai Hähnle
2017-06-19 15:12:57 UTC
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Post by Marek Olšák
Post by Nicolai Hähnle
Post by Marek Olšák
GFX9 is affected.
---
src/gallium/drivers/radeonsi/si_blit.c | 36
++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/si_blit.c
b/src/gallium/drivers/radeonsi/si_blit.c
index 1159594..b78fddf 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -1133,20 +1133,56 @@ void si_resource_copy_region(struct pipe_context *ctx,
src_templ.format =
PIPE_FORMAT_R32G32B32A32_UINT;
break;
fprintf(stderr, "Unhandled format %s with
blocksize %u\n",
util_format_short_name(src->format), blocksize);
assert(0);
}
}
}
+ /* SNORM8 blitting has precision issues on some chips. Use the
SINT
+ * equivalent instead, which doesn't force DCC decompression.
+ * Note that some chips avoid this issue by using SDMA.
+ */
+ if (util_format_is_snorm8(dst_templ.format)) {
+ switch (dst_templ.format) {
+ dst_templ.format = src_templ.format =
PIPE_FORMAT_R8_SINT;
+ break;
+ dst_templ.format = src_templ.format =
PIPE_FORMAT_R8G8_SINT;
+ break;
+ dst_templ.format = src_templ.format =
PIPE_FORMAT_R8G8B8X8_SINT;
+ break;
+ case PIPE_FORMAT_A8B8G8R8_SNORM: /* also swizzle */
+ case PIPE_FORMAT_X8B8G8R8_SNORM: /* also swizzle */
+ dst_templ.format = src_templ.format =
PIPE_FORMAT_R8G8B8A8_SINT;
Why does R8G8B8X8 need a separate case but not X8B8G8R8?
There are no SINT variants for ABGR and XBGR, so we have to use RGBA.
Okay I guess, since it's anyway just resource_copy_region.
Post by Marek Olšák
Post by Nicolai Hähnle
Do we have a test for this?
We only have tests for GL_x_SNORM where x is R8, RG8, RGB8, and RGBA8.
Marek
--
Lerne, wie die Welt wirklich ist,
Aber vergiss niemals, wie sie sein sollte.
Marek Olšák
2017-06-17 13:44:33 UTC
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From: Marek Olšák <***@amd.com>

---
src/amd/common/gfx9d.h | 4 ++--
src/gallium/drivers/radeonsi/si_state.c | 6 ++++++
2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/gfx9d.h b/src/amd/common/gfx9d.h
index 787d0a9..8c61645 100644
--- a/src/amd/common/gfx9d.h
+++ b/src/amd/common/gfx9d.h
@@ -1338,22 +1338,22 @@
#define V_008F14_IMG_DATA_FORMAT_ASTC_3D_LDR 0x31 /* ditto */
#define V_008F14_IMG_DATA_FORMAT_ASTC_3D_HDR 0x32 /* ditto */
#define V_008F14_IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB 0x33 /* ditto */
#define V_008F14_IMG_DATA_FORMAT_N_IN_16 0x34
#define V_008F14_IMG_DATA_FORMAT_N_IN_16_16 0x35
#define V_008F14_IMG_DATA_FORMAT_N_IN_16_16_16_16 0x36
#define V_008F14_IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16 0x37
#define V_008F14_IMG_DATA_FORMAT_RESERVED_56 0x38
#define V_008F14_IMG_DATA_FORMAT_4_4 0x39
#define V_008F14_IMG_DATA_FORMAT_6_5_5 0x3A
-#define V_008F14_IMG_DATA_S8_16 0x3B
-#define V_008F14_IMG_DATA_S8_32 0x3C
+#define V_008F14_IMG_DATA_FORMAT_S8_16 0x3B
+#define V_008F14_IMG_DATA_FORMAT_S8_32 0x3C
#define V_008F14_IMG_DATA_FORMAT_8_AS_32 0x3D
#define V_008F14_IMG_DATA_FORMAT_8_AS_32_32 0x3E
#define V_008F14_IMG_DATA_FORMAT_32_AS_32_32_32_32 0x3F
#define S_008F14_NUM_FORMAT_GFX9(x) (((unsigned)(x) & 0x0F) << 26)
#define G_008F14_NUM_FORMAT_GFX9(x) (((x) >> 26) & 0x0F)
#define C_008F14_NUM_FORMAT_GFX9 0xC3FFFFFF
#define V_008F14_IMG_NUM_FORMAT_UNORM 0x00
#define V_008F14_IMG_NUM_FORMAT_SNORM 0x01
#define V_008F14_IMG_NUM_FORMAT_USCALED 0x02
#define V_008F14_IMG_NUM_FORMAT_SSCALED 0x03
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 2a2c3c0..921f374 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3239,20 +3239,26 @@ si_make_texture_descriptor(struct si_screen *screen,

/* Enable clamping for UNORM depth formats promoted to Z32F. */
if (screen->b.chip_class >= GFX9 &&
util_format_has_depth(desc) &&
num_format == V_008F14_IMG_NUM_FORMAT_FLOAT &&
util_get_depth_format_type(base_desc) != UTIL_FORMAT_TYPE_FLOAT) {
/* NUM_FORMAT=FLOAT and DATA_FORMAT=24_8 means "clamp to [0,1]". */
data_format = V_008F14_IMG_DATA_FORMAT_24_8;
}

+ /* S8 with Z32 HTILE needs a special format. */
+ if (screen->b.chip_class >= GFX9 &&
+ pipe_format == PIPE_FORMAT_S8_UINT &&
+ tex->tc_compatible_htile)
+ data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
+
if (!sampler &&
(res->target == PIPE_TEXTURE_CUBE ||
res->target == PIPE_TEXTURE_CUBE_ARRAY ||
(screen->b.chip_class <= VI &&
res->target == PIPE_TEXTURE_3D))) {
/* For the purpose of shader images, treat cube maps and 3D
* textures as 2D arrays. For 3D textures, the address
* calculations for mipmaps are different, so we rely on the
* caller to effectively disable mipmaps.
*/
--
2.7.4
Nicolai Hähnle
2017-06-19 12:56:19 UTC
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Post by Marek Olšák
---
src/amd/common/gfx9d.h | 4 ++--
src/gallium/drivers/radeonsi/si_state.c | 6 ++++++
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/amd/common/gfx9d.h b/src/amd/common/gfx9d.h
index 787d0a9..8c61645 100644
--- a/src/amd/common/gfx9d.h
+++ b/src/amd/common/gfx9d.h
@@ -1338,22 +1338,22 @@
#define V_008F14_IMG_DATA_FORMAT_ASTC_3D_LDR 0x31 /* ditto */
#define V_008F14_IMG_DATA_FORMAT_ASTC_3D_HDR 0x32 /* ditto */
#define V_008F14_IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB 0x33 /* ditto */
#define V_008F14_IMG_DATA_FORMAT_N_IN_16 0x34
#define V_008F14_IMG_DATA_FORMAT_N_IN_16_16 0x35
#define V_008F14_IMG_DATA_FORMAT_N_IN_16_16_16_16 0x36
#define V_008F14_IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16 0x37
#define V_008F14_IMG_DATA_FORMAT_RESERVED_56 0x38
#define V_008F14_IMG_DATA_FORMAT_4_4 0x39
#define V_008F14_IMG_DATA_FORMAT_6_5_5 0x3A
-#define V_008F14_IMG_DATA_S8_16 0x3B
-#define V_008F14_IMG_DATA_S8_32 0x3C
+#define V_008F14_IMG_DATA_FORMAT_S8_16 0x3B
+#define V_008F14_IMG_DATA_FORMAT_S8_32 0x3C
#define V_008F14_IMG_DATA_FORMAT_8_AS_32 0x3D
#define V_008F14_IMG_DATA_FORMAT_8_AS_32_32 0x3E
#define V_008F14_IMG_DATA_FORMAT_32_AS_32_32_32_32 0x3F
#define S_008F14_NUM_FORMAT_GFX9(x) (((unsigned)(x) & 0x0F) << 26)
#define G_008F14_NUM_FORMAT_GFX9(x) (((x) >> 26) & 0x0F)
#define C_008F14_NUM_FORMAT_GFX9 0xC3FFFFFF
#define V_008F14_IMG_NUM_FORMAT_UNORM 0x00
#define V_008F14_IMG_NUM_FORMAT_SNORM 0x01
#define V_008F14_IMG_NUM_FORMAT_USCALED 0x02
#define V_008F14_IMG_NUM_FORMAT_SSCALED 0x03
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 2a2c3c0..921f374 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3239,20 +3239,26 @@ si_make_texture_descriptor(struct si_screen *screen,
/* Enable clamping for UNORM depth formats promoted to Z32F. */
if (screen->b.chip_class >= GFX9 &&
util_format_has_depth(desc) &&
num_format == V_008F14_IMG_NUM_FORMAT_FLOAT &&
util_get_depth_format_type(base_desc) != UTIL_FORMAT_TYPE_FLOAT) {
/* NUM_FORMAT=FLOAT and DATA_FORMAT=24_8 means "clamp to [0,1]". */
data_format = V_008F14_IMG_DATA_FORMAT_24_8;
}
+ /* S8 with Z32 HTILE needs a special format. */
+ if (screen->b.chip_class >= GFX9 &&
+ pipe_format == PIPE_FORMAT_S8_UINT &&
+ tex->tc_compatible_htile)
+ data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
+
if (!sampler &&
(res->target == PIPE_TEXTURE_CUBE ||
res->target == PIPE_TEXTURE_CUBE_ARRAY ||
(screen->b.chip_class <= VI &&
res->target == PIPE_TEXTURE_3D))) {
/* For the purpose of shader images, treat cube maps and 3D
* textures as 2D arrays. For 3D textures, the address
* calculations for mipmaps are different, so we rely on the
* caller to effectively disable mipmaps.
*/
--
Lerne, wie die Welt wirklich ist,
Aber vergiss niemals, wie sie sein sollte.
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